<?xml version="1.0" encoding="UTF-8"?>
<SOFTPKG NAME="Hardware-Verilog-Parser" VERSION="0,13,0,0">
  <TITLE>Hardware-Verilog-Parser</TITLE>
  <ABSTRACT>A complete grammar for parsing Verilog code using perl</ABSTRACT>
  <AUTHOR>Greg London &lt;GSLONDON@cpan.org&gt; </AUTHOR>
  <IMPLEMENTATION>
    <OS NAME="MSWin32" />
    <ARCHITECTURE NAME="MSWin32-x86-multi-thread-5.10" />
    <CODEBASE HREF="MSWin32-x86-multi-thread-5.10/Hardware-Verilog-Parser-0.13.zip" />
    <PROVIDE NAME="Hardware::Verilog::Hierarchy" VERSION="0.03" />
    <PROVIDE NAME="Hardware::Verilog::Parser" VERSION="0.13" />
    <PROVIDE NAME="Hardware::Verilog::StdLogic" VERSION="0.03" />
  </IMPLEMENTATION>
</SOFTPKG>

